Solid state imagers often employ charge coupled devices. A particularly well-known such imager is the field transfer type CCD imager. In this imager a radiant energy image is projected during image integration intervals into an image (or A) register comprising a plurality of parallel charge transfer channels. These image integration intervals occur during the field trace portions of video signal generated from video signal samples supplied from the imager as output signal. During these image integration intervals static clocking signals are applied to the parallel charge transfer channels in the A register. Charge generated by photoconversion of the radiant energy image, either in these charge transfer channels or the underlying bulk semiconductor, is accumulated in charge packets representative of the intensities of respective elements of the radiant energy image. These charge packets are accumulated in the respective charge transfer stages of A register charge transfer channels.
During field transfer intervals, which occur during the field retrace portions of video signal, dynamic clocking signals are applied to the parallel charge transfer channels in the A register to transfer the accumulated charge packets serially out of each charge transfer channel. The charge packets are transferred serially into corresponding ones of the parallelled charge transfer channels of a field storage (or B) register, which is shielded from exposure to radiant energy. This field transfer is accomplished in prior field transfer type CCD imagers by foward clocking the A and B registers in synchronism with each other.
During the field trace portion of video signal following each field transfer, the charge packets, accumulated during the preceding field trace and subsequently transferred to the B register, are transferred out of the B register in the following way. During each line retrace interval the B register is forward clocked to advance all charge packets stored therein ahead one charge transfer stage, transferring out the previously last row of charge packets stored therein, which row represents a line of image element samples to be converted into a line of video signal output voltage samples. Towards this end, the row of charge packets displaced from B register during line retrace are loaded in parallel into respective charge transfer stages of a charge transfer channel operated as an output line (or C) register.
During line trace the C register is forward clocked at pixel scan rate, as a CCD shift register, to convert the row of parallelly loaded charge packets to a serial-in-time format. The charge packets serially supplied at pixel scan rate from the C register are supplied to a charge sensing output stage, or electrometer. This output stage responds to the charge packets to provide, in conventional raster scan order, video output signal samples related to the intensity of radiant energy image elements.
There is a desire for obtaining higher resolution in CCD imagers, which can be satisfied in a practical way using the state-of-the-art processing limitations on maximum die sizes and on minimum element sizes only if one uses a plurality of abutted CCD imagers. CCD imagers of field transfer type could be readily abutted in the direction of line scan--since their A, B and C registers can be confined within a pair of boundaries flanking the parallelled charge transfer channels of the A and B registers--if it were not for the difficulty that the charge sensing stage at the output end of the C register extends beyond one of the boundaries. It has been proposed to solve the problem of the overextending charge sensor stage by introducing a narrowing of the charge transfer channels of the B register along a portion of their lengths, so a shorter C register can be used. The shortened C register and the ensuing charge sensing stage can then be readily confined within the two boundaries flanking the sides of the A and B registers.
The narrowing of the final portions of the B register charge channels, or their gradual narrowing over their entire length, tends to reduce the charge handling capability of the charge transfer channels in their narrower portions.
One may attempt to solve this problem by increasing potential energy well depth in the narrower portions of the charge transfer channels by increasing gate electrode clocking voltage swing. To increase clocking voltage swing for the entire B register is costly in terms of clocking power, and to increase clocking voltage swing only over a portion of the B register introduces undesirable complexity into clocking voltage generation. Either scheme goes against the current desire to reduce clocking voltage clocking power to ease clock driver transistor requirements.
One may attempt to increase charge handling capability of the narrower portions of the B register charge transfer channels by lengthening the "pitch", the length of the charge transfer stage, by increasing the lengths of the gate electrodes in each charge transfer stage. But this reduces the maximum rate at which efficient charge transfer through the B register can be made, and undesirably increases the duration of field transfer.
One may attempt to increase the charge handling capability of the charge transfer stages in the narrower portions of the B register together with the preceding charge transfer stages in the A and B registers, by increasing the number of clocking signal phases in both registers. This has the problem that for given minimum gate length and pixel resolution requirement in the direction of line advance, the A register size is increased, requiring the optics systems that convey the image to the A register to convey a larger image. The increased A register and B register size for given minimum gate length and pixel resolution requirement takes up a larger semiconductor die, which is undesirable from the standpoint of semiconductor manufacturing usable yield.